Pre lab 7: 1. (a) A D flip-flop using 5 NAND gates (b) A D flip-flop using 4 NAND gates (c) Using P spice he following outputs are obtained for both the D flip-flops constructed in a and b. Figure a: Output for D flip-flop with 5 NAND gates Figure b: Output for D flip-flop with 4 NAND gates By comparison of the outputs of the D flip-flops constructed in a and b using 5 and 4 NAND gates we can see they operate the same way. 2. (a) The logic diagram of the circuit: A (t+1) = x’ (t) y (t) + x (t) A (t) B (t+1) = x’ (t) B (t) + x (t) A (t) z = B (t) 2. (b) The state table: A (t) B (t) x y A (t+1) B (t+1) z 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 0 1 1 1 1 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 4.
DIFFERENCE BETWEEN PARALLEL & SERIAL DATA: There are two methods of transmitting digital data. These methods are parallel and serial transmissions. In parallel data transmission, all bits of the binary data are transmitted simultaneously. For example, to transmit an 8-bit binary number in parallel from one unit to another, eight transmission lines are required.
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Objective To complete all aspects of the exercise regarding D type flip-flop, TTL and CMOS and to familiarize us with the HDL software which is Mentor Graphics. This software is capable of constructing and simulating a particular design. As for this assignment 1, we are given 4 weeks to complete the assignment. It is compulsory to attend every lab sessions as there is no alternative software to ...
Each bit requires its own separate data path. All bits of a word are transmitted at the same time. This method of transmission can move a significant amount of data in a given period of time. Its disadvantage is the large number of interconnecting cables between the two units. For large binary words, cabling becomes complex and expensive. This is particularly true if the distance between the two units is great.
Long multi word cables are not only expensive, but also require special interfacing to minimize noise and distortion problems. serial data transmission is the process of transmitting binary words a bit at a time. Since the bits time-share the transmission medium, only one interconnecting lead is required. While serial data transmission is much simpler and less expensive because of the use of a single interconnecting line, it is a very slow method of data transmission. Serial data transmission is useful in systems where high speed is not a requirement. Serial data transmission techniques are widely used in transmitting data between a computer and its peripheral units.
Lab Report 7 Parallel-to-serial conversion Implementation of a parallel-to-serial data conversion logic for eight input parallel data line using the 74 LS 151 Multiplexer IC and other available ICs and components. Implement a circuit to generate the signals for the DATA SELECT inputs (A, B and C) of the 74 LS 151 Multiplexer. a. The generated signals A, B and C should be 250 Hz, 125 Hz and 62. 5 Hz respectively. b.
Make two hardcopies for the signals A (CH 1) & B (CH 2) and B (CH 1) & C (CH 2).
The hardcopy should indicate the frequency and the period of each signal. When we design the circuit we make special use of the datasheets provided in the laboratory. Provided datasheets are for the 74 LS 151 Multiplexer, for the 2 input AND gate and for the Dual Negative Edge- Triggered Master Slave J-K Flip Flop.
The parallel to serial conversion serial conversion is implemented using a circuit based on the 74 LS 151 multiplexer and the 3 bits binary counter. We are using this circuit, as we are instructed in the question that we should achieve an output of three halved signals with regard to frequencies. This is the output of the 3-bits counter circuit using the JK Flip Flop. fig 1. input / output of a 3-bit binary counter Our circuit: The above circuit will be connected to the Multiplexer. We will be connecting the output of these three flip flops to the data select inputs of the Multiplexer: fig.
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Abstract This paper will discuss the design of an FM receiver. It will begin with a brief historical backdrop of FM broadcasting and its use in society. It will continue by providing the necessary mathematical background of the modulation process. Furthermore, it will enumerate some of the advantages of FM over other forms of modulation, namely AM. Finally, the paper will discuss the design of a ...
2. connection diagram for a multiplexer. fig 3. connection diagram for the JK flip flop. fig.
4 connection diagram of the 2 Input AND gate Using the connection diagram of the multiplexer, the 2 input AND gate and the JK Flip Flop, we connected the binary counter circuit to the multiplexer and to the oscilloscope to see output of the two signals one by one, once signal A and B, and then B and C. The oscilloscope has been applied a 2. 5 Vpp and also a 1. 2 DC Offset in order to remove the distortions. The two hardcopies of these three signals are provided here: As one can see clearly, the frequency of the first signal, channel 1- signal A, has 250 Hz, while the second one has its frequency halved due to the operation of the JK flip flops in the 3 bit counter circuit. Also, we see that while the period of the first signal is 4.
00 ms the second one has double the period of the first signal which is in accordance with the relationship between frequency and period: F = 1/T. Once the period decreases, the frequency increases and vice versa. For signals B and C, we have attached another hardcopy: Here, we can see that the frequency of the last signal has halved again with respect to the second signal, from 125 Hz to 62. 5 Hz, which is again what we desired when we applied the 3 bit counter circuit. And again we see that the period of the last signal has doubled with respect to signal B, following the relationship f = 1/T. As indicated in the instruction sheet, an instructor or teaching assistant has been called and did verify the circuit of proper functioning.
For our second problem, we are instructed to: a. Use the circuit implemented in (1. ) to form the complete circuit of a parallel-to-serial data conversion logic for eight input parallel data line. b. Choose reasonable frequencies for the DATA SELECT inputs (frequencies to have stable signals on the oscilloscope screen) and make a hardcopy for A (CH 1) and the output converted serial data Y (CH 2).
The Term Paper on Input And Output Devices And Computer Components
The purpose of this paper is to answer questions about various data input and output methods, various storage types and devices, and the speed of a computer. Each of the four questions is divided into a corresponding section below. In the input device section, this paper focuses primarily on user input, rather than the input devices used to extract information entered by a user. In all of the ...
Use the following eight bits input parallel data 11011001.
c. Use LED indicators to indicate the data selection inputs (DATA SELECT inputs) and the converted output serial data (Y).
Choose reasonable frequencies for the DATA SELECT inputs (frequencies so that the instructor or teaching assistant can observe the change of the output converted serial data with the change of DATA SELECT inputs).
The complete circuit of a parallel-to-serial data conversion logic has been implemented by using the circuit in problem 1 and adding the data inputs from the multiplexer, which are selected with preference. In our case, the sequence of the data inputs is given by the following eight bits input parallel data: 11011001.
Thus, we connect the inputs to either high or low (Vcc or ground).
Taking another look at the connection diagram of the multiplexer: we see which is the start of the data inputs and which ones should be connected to either high or low. Also, we see that our output will be connected to the Y pin and to the A pin data select. The strobe has to be taken in consideration, and we connect that to low, so that our Y output will be high. After connecting the Y pin output and the A pin data select to the oscilloscope, we see this image: From this hardcopy, we see that while the input signal has a very high frequency, while the output signal follows closely the input parallel data sequence: 11011001.
We see this by following the output (CH 2), starting with the first wider rectangular part: high, high, low, high, high, low, low, and high. After this, the next sequence comes and repeats itself. For the third point, we connect the 4 LEDs in series with the first inputs, respectively with the output as well, and we see that indeed they indicate the sequence 11011001, seen in the hardcopy as well. As indicated in the instruction sheet, an instructor or teaching assistant has been called to verify that the circuit worked.
